Encapsulated MoS2 FETs with Improved Performance and Reliability

Considerable progress in the fabrication of MoS2 FETs has been demonstrated recently [1]. However, available device prototypes still suffer from a sizable hysteresis of the ID-VG characteristics [2,3] and long-term drifts of threshold voltage Vth [3,4], known as bias-temperature instabilities (BTI). As such, these issues must be addressed prior to commercialization of MoS2 technologies. Here we report on the improvement of the properties of MoS2/SiO2(25 nm) FETs [5] introduced by the encapsulation with high-quality Al2O3(15 nm) based on a modified recipe of [6]. The Ion/Ioff ratio of these devices is as high as 10 9 (Fig.1a), which is already close to predicted values [7]. At the same time, the hysteresis is two orders of magnitude smaller than in bare exfoliated devices (Fig.1b). Furthermore, positive BTI (PBTI) in encapsulated CVD devices is weakly pronounced (Fig.1c), which is important for MoS2 n-FETs. Quite remarkably, PBTI is weaker than in previously reported exfoliated bare MoS2/SiO2 [3], stacked MoS2/hBN [3] and encapsulated BP/SiO2 FETs [8] (Fig.1d). The reason for the reduced hysteresis and BTI, as well as for the improved device perfromance, is that the encapsulation layer efficiently protects the device from adsorbent-type trapping sites on top of the MoS2 channel [3].